[Pw_forum] Seeking Advice on Small Hardware Platforms for PWscf Implementation

Axel Kohlmeyer akohlmey at cmm.chem.upenn.edu
Thu Nov 22 06:25:44 CET 2007


On Tue, 20 Nov 2007, Paul M. Grant wrote:

PG> Thanks for the feedback.  The two dual Xeon boards I have were originally
PG> chosen to host my website.  I long suspected that there was "thrashing"
PG> between the two processors when performing numerically intensive
PG> calculations.  I assume the same would occur within the cores of a single
PG> processor as well?  However, my understanding was this approach was supposed
PG> to better implement matrix manipulation for gaming applications.  If so, one
PG> would assume improved performance for the fft operations at the "core" of
PG> pw.x.

paul,

you have to be careful to not compare apples and oranges.
older xeons (netburst arch), particularly the 2.4GHz ones
were notorius for over saturating memory bandwidth with even
a single core (hence the significant step up of cache for
the xeon variety over desktop version and double cache increase
for the 4-way versions). those actually get slower with using
both cpus for memory intensive applications. i have some benchmark
numbers with CPMD (same as QE it uses plane waves and psps)
on my (mostly obsolete) homepage in bochum.

current, "core" xeons are _much_ better and also the memory
bus has improved a lot since. the "trashing" is of minor importance.
it the actively used memory subset that counts. if it fits into
the cache the cpu is very fast, if not, it is horribly slow
(in two way config). 

cheers,
  axel.

PG> 
PG> Paul M. Grant, PhD
PG> Principal, W2AGZ Technologies
PG> Visiting Scholar, Applied Physics, Stanford University
PG> EPRI Science Fellow (Retired)
PG> IBM Research Staff Member Emeritus
PG> w2agz at pacbell.net
PG> http://www.w2agz.com
PG>  
PG>  
PG> 
PG> -----Original Message-----
PG> From: pw_forum-bounces at pwscf.org [mailto:pw_forum-bounces at pwscf.org] On
PG> Behalf Of Alexander Shaposhnikov
PG> Sent: Tuesday, November 20, 2007 1:02 AM
PG> To: PWSCF Forum
PG> Subject: Re: [Pw_forum] Seeking Advice on Small Hardware Platforms for PWscf
PG> Implementation
PG> 
PG> Actually newer  Woodcrest/Clovertown Xeon platform  have dual independent 
PG> FSBs, but this does not help much. Memory bandwidth available on each FSB is
PG> 
PG> very limited - between  1/2 and 1/3  of what is available to modern desktop 
PG> CPUs.
PG> 
PG> There is no good "server" computational platform today,  unfortunately  . 
PG> AMD's CPUs have  weak FPU  and Intel's have weak memory subsystem. Intel- 
PG> based desktop single-socket platform is the best choice for now.
PG> 
PG> On Tuesday 20 November 2007 14:33, Paolo Giannozzi wrote:
PG> > On Nov 20, 2007, at 4:07 , Paul M. Grant wrote:
PG> > >  Currently, I use two machines with dual Xeon processors
PG> >
PG> > dual Xeon? very bad choice. They have a single memory
PG> > bus, so if you run two processes on the same motherboard,
PG> > they spend most of the time waiting for access to memory.
PG> >
PG> > P.
PG> > ---
PG> > Paolo Giannozzi, Dept of Physics, University of Udine
PG> > via delle Scienze 208, 33100 Udine, Italy
PG> > Phone +39-0432-558216, fax +39-0432-558222
PG> >
PG> >
PG> >
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-- 
=======================================================================
Axel Kohlmeyer   akohlmey at cmm.chem.upenn.edu   http://www.cmm.upenn.edu
   Center for Molecular Modeling   --   University of Pennsylvania
Department of Chemistry, 231 S.34th Street, Philadelphia, PA 19104-6323
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